This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-277125, filed Sep. 12, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor apparatus pattern and more particularly to a method of effectively inspecting and evaluating critical locations on a semiconductor apparatus pattern especially having partially thick or thin shapes.
2. Description of the Related Art
Locating and analyzing a semiconductor apparatus pattern defect needs information (defect information) such as a defect coordinate obtained from a defect inspection apparatus and the like. One coordinate is given to one defect. During defect analysis, the defect inspection apparatus is supplied with a pattern and a corresponding defect coordinate. A defect is retrieved on the pattern based on the defect coordinate.
A general defect is easily located because it causes an abnormal state differing from adjacent pattern portions such as pattern opening or short-circuiting, particles, and the like. In the case of general defects, it is possible to easily obtain a defect image and measure the dimensions. Consequently, the defect can be easily analyzed.
However, there arises a problem in the case of partial thickening or thinning, shortening with only one end of a pattern shortened, and the like. Even if the sample is searched based on the defect coordinate, it is difficult to visually locate and analyze a critical location except in extreme cases.
Unlike an abnormal defect such as pattern opening or short-circuiting, and the like, the critical location is not easily determined whether as a defect until sandwiching wiring layers are actually formed.
As mentioned above, partial thickening or thinning, shortening with only one end of a pattern shortened, and the like cause the problem that it is impossible to easily pinpoint the critical location even if a defect is searched based on the defect coordinate (defect information).
According to the present invention, there is provided a critical location evaluation method for a semiconductor apparatus pattern, comprising: comparing first pattern data corresponding to no critical location with second pattern data corresponding to a critical location with respect to the same semiconductor apparatus pattern; and extracting a difference between the first pattern data and the second pattern data as information indicating a characteristic of the critical location, with respect to a location causing the difference.